The primer explicitly compares HLS versus RTL approaches, noting that while HLS accelerates design, RTL provides ultimate control.
Using tools like Vivado Simulator to verify mathematical correctness before hardware implementation.
You then measure:
Modern Xilinx FPGAs (Series 7, UltraScale, Versal) contain dedicated slices. The Primer doesn't treat them as black boxes. It explores: Xilinx University Program - DSP for FPGA Primer...
The Xilinx University Program emphasizes a tiered design methodology, moving from high-level abstractions down to hardware description languages.
The primer includes labs where you write a C++ FIR filter, add pragmas like #pragma HLS PIPELINE or #pragma HLS UNROLL , and watch the tool generate a parallel datapath.
Process giga-samples per second (GSPS) directly from analog-to-digital converters (ADCs). 2. Core Architectural Element: The DSP Micro-Architecture The primer explicitly compares HLS versus RTL approaches,
Entry-level digital logic and introductory hardware-based DSP labs. Zynq-7000 SoC
The XUP primer assumes you work within the Xilinx ecosystem. Here’s the typical workflow:
A typical 32-tap FIR filter on a 200 MHz ARM Cortex-M takes ~32 cycles per sample. On an FPGA using the XUP primer’s systolic architecture, it takes 1 clock cycle for all 32 taps. That’s a 32x speedup—without increasing clock frequency. The Primer doesn't treat them as black boxes
In a microprocessor, you write code that executes step-by-step. In an FPGA, you create the hardware —thousands of multiply-accumulate units running in parallel, each dedicated to one job.
IIR filters use feedback to achieve sharper cutoff characteristics with fewer coefficients than FIR filters. Because they rely on past outputs, they are susceptible to quantization errors and potential instability. FPGA implementations require careful bit-width planning in the feedback loop to avoid limit cycles and overflow. Fast Fourier Transform (FFT)